Command user interface with programmable decoder

ABSTRACT

A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

RELATED APPLICATION

This Application is a Contination of U.S. application Ser. No.10/703,322, filed Nov. 7, 2003 (allowed), and titled COMMAND USERINTERFACE WITH PROGRAMMABLE DECODER, which is a Divisional of U.S.application Ser. No. 10/050,475 filed Jan. 15, 2002 and titled, “COMMANDUSER INTERFACE WITH PROGRAMMABLE DECODER” (now U.S. Pat. No. 6,757,872,issued Jun. 29, 2004), which is incorporated herein by reference, whichclaims priority to Italian Application No. RM001A000298 filed May 31,2001 (now Italian Patent No. 0001323331, issued Aug. 16, 2004), all ofwhich are commonly assigned.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to ROM operation, and morespecifically to a programmable via mask for ROM encoding.

BACKGROUND

Decoders are used in read only memories to decode input data forpresentation to the ROM to allow the ROM to execute an operationprogrammed into the ROM if the proper input sequence of data ispresented.

There are several problems with making a decoders. In some decoders, amicrocontroller gives a sequence or coding to enter a specific operationwhich is encoded into a read only memory (ROM) and the enablingcircuitry for the ROM. Such specific operations include by way ofexample read array, read configuration register, program, erase,suspend, and the like.

A command user interface (CUI) is a state machine that recognizesmulti-cycle microprocessor commands. The commands are entered usingmulti-clock cycle operations. For each cycle, the CUI changes statedepending upon the current inputs and the decoding of the previous stateof the system. A typical CUI implementation is one which is based inlogic gate network syntheses starting from circuit equations andautomated layout generation. While this method provides fast solutionsfor layout generation, it is very inflexible. If even one commandequation changes, the entire circuit layout and subsequent generationflow must also be re-executed. This results in significant delays inproduction. When delays in production occur, money is lost.

Common state machines used for decoding include Mealy and Moore Modelstate machines.

SUMMARY

In one embodiment, a command user interface includes a decoder having aseries of transistors whose gates are selectively coupled to receiveeither an input or its complement using vias, a read only memory, and anumber of latches to latch input and output data for the command userinterface.

In another embodiment, a programmable decoder includes a first decodersection having a number of transistors connected in series. The gates ofthe transistors are selectively coupled to receive either an input orits complement from one of a pair of contacts. Each contact is coupledto the input or to the complement of the input.

In another embodiment, a method of changing a command definition of adecoder includes changing only via locations in an insulating layer,wherein a via location defines a contact to which a gate of a transistoris coupled.

In yet another embodiment, a method of programming a decoder includesfabricating a number of series connected transistors, and fabricating apair of contacts for each transistor. Each contact is hard wired toeither an input or a complement of the input, and the gate of eachtransistor is selectively coupled to one of its pair of contacts.

Other embodiments are described and claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of the present invention;

FIG. 2 is a circuit diagram of a portion of another embodiment of thepresent invention;

FIG. 2A is a circuit diagram of another embodiment of the presentinvention;

FIG. 3 is a timing diagram of a timing sequence of an embodiment of thepresent invention; and

FIG. 4 is a flow chart diagram of a method according to anotherembodiment of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the embodiments, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown by way of illustration specific embodiments in which theinvention may be practiced. It is to be understood that otherembodiments may be utilized and structural or logical changes may bemade without departing from the scope of the present invention.

FIG. 1 is a block diagram of a command user interface (CUI) 100according to one embodiment of the present invention. CUI 100 comprisesin one embodiment a series of latches 102, a read only memory (ROM) 104,and a decoder 106. The latches 102 comprise in one embodiment synchlatches 108 and status latches 110. The decoder 106 in one embodimentcomprises three sections, a status section 112, a DQ command section114, and a feedback section 116. The input synch latches 108 a receiveincoming signals comprising clock signals, incoming data inputs, andfeedback from a write state machine (WSM). The input synch latches 108 aoutput outgoing signals including a latched DQ command code and latchedfeedback output control, to the decoder 106 and external chip circuitry,respectively. Output synch latches 108 b receive output from ROM 104,and output commands externally. Status latch 110 receives statusinformation from ROM 104 and latches it to decoder 106.

The inputs to the CUI 100 in one embodiment are a clock signal CLK tosynchronize operation, and a command code COM. The clock signal servesto synchronize operation of the system 100. In one embodiment, the clocksignal is a combination of a write enable WE* (active low) signal and achip enable CE* (active low) signal. The command code COM is in oneembodiment an 8 bit command code issued by a user and is input to thesystem 100 through DQ pins (not shown). In the system 100, the user'scommands indicate a desired operation to be performed by a ROM such asROM 104. A specific operation is programmed or encoded into the ROM 104through encoding which is described in further detail later.

If the operation programmed into the ROM 104 and the operation indicatedby the user supplied data are the same, the operation is performed bythe ROM 104. If the desired operation and the programmed operationdiffer, then there is an error situation.

The CUI 100 is a state machine that recognizes multi-cyclemicroprocessor commands. The command user interface in one embodimentinterprets the commands sent into the system, usually by a user. Thecommands are entered using multi-clock cycle operations. For each cycle,the CUI changes state depending upon the current inputs and the decodingof the previous state of the system. For each state, the CUI generatesthe proper outputs which are sent to a write state machine (WSM), thusdelegating the WSM to take over control of the execution of the currentalgorithm.

A decoder in one embodiment of the present invention is arranged inthree sections, a status section, a DQ command section, and a feedbackdecoder section. Data sent in to the CUI from outside into the ROM isfed to the synchronizing latches to synch with the system clocks.

The decoding is performed with a decoder such as decoder 106 to decodedata input to the ROM, with latches such as latches 108 and 110 to storevarious data and other information from the ROM, and with controlcircuitry for implementing timing for the system. The decoder such asdecoder 106 accepts as inputs in one embodiment a command code from thesynch latches 108, a series of feedback signals from external to thedecoder chip circuitry, and a status code from the status latches. Inone embodiment, the command code is an 8 bit command code. In oneembodiment, the series of feedback signals are sent from severalcircuitries of the CUI, including in various embodiments charge pumps,WSMs, analog blocks, and the like. The feedback signals provide the CUIinformation about the status of the circuitry controlled by the CUI. Inone embodiment, the status code is an 8 bit status code.

The inputs are in one embodiment parallel decoded by a decoder such asdecoder 106. The input data is fed to the decoder through latches suchas synch latches 108. In one embodiment, the decoder decodes the inputsbased on the current status of the ROM, feedback signals from externalchip circuitry, and the current inputs. When the inputs are decoded,they are presented to the ROM 104. If what is encoded into the ROM 104matches the decoded inputs, then the specific operation written in theROM 104 is performed. If what is encoded into the ROM 104 does not matchthe decoded inputs, then an error situation exists.

In order for the ROM decoder 106 to function, the ROM must first beencoded. Each of the signals sent to the decoder is in one embodimentdecoded in its own separate section of the decoder. Each decoder sectionin one embodiment comprises a series of blocks of transistors whichdecode individual bits of data. Such blocks are described in furtherdetail below. In one embodiment, the blocks are each programmable so asto allow for easy programming and therefore encoding. In one embodiment,each byte of a command series is decoded using a section of the decoder106.

A portion of the decoder 106 is shown in greater detail in FIG. 2.Decoder 106 comprises in one embodiment a series of blocks such as block200. Each of the blocks decodes one of the input signal combinations.Each block comprises in one embodiment a series connection of eighttransistors, configured to recognize a specific single 8 bit inputconfiguration.

Block 200 comprises a series connection of eight transistors 202, 204,206, 208, 210, 212, 214, and 216. The series of transistors is in oneembodiment a series of N type transistors. The series of transistors isenabled by transistor 218 having its gate connected to a ROM_READsignal. Each of the transistors 202, 204, 206, 208, 210, 212, 214, and216 has its gate selectively connected, using interconnects 221, 223,225, 227, 229, 231, 233, and 235, to one of a pair or more of viasaccessing contacts 220, 222, 224, 226, 228, 230, 232, and 234respectively. Note that each of contacts 220, 222, 224, 226, 228, 230,232, and 234 includes at least a pair of contact elements, e.g., whereinterconnect 221 selectively engages the pair of contact elements ofcontact 220, interconnect 223 the pair of contact elements of contact222, interconnect 225 the pair of contact elements of contact 224,interconnect 227 the pair of contact elements of contact 226,interconnect 229 the pair of contact elements of contact 228,interconnect 231 the pair of contact elements of contact 230,interconnect 233 the pair of contact elements of contact 232, andinterconnect 235 the pair of contact elements of contact 234, as shownin FIG. 2. The contacts are coupled to a bus 236 carrying all the statusinputs to the system (status), or to a bus 238 carrying all of thecomplements of the status inputs of the system (statusb).

Further, in another embodiment, the contacts 220 and 234 are alsocoupled directly to a supply voltage for the system via connection lines240. This connection configures the 202 and 216 transistor locations as“don't cares,” meaning that either a binary high or a binary low isacceptable for the configuration. The outcome from the decoder foreither state is therefore the same.

Each transistor in one embodiment is capable of being programmed toconnect the gate either to a logic 1 or a logic 0 through its respectivevia and contact. This connection is made in one embodiment through viaprogramming techniques to one input or the inverted value of the input,such that a transistor/contact combination can in various configurationsrecognize either the 0 or the 1 logic value of the input bit. In anotherembodiment, two of the eight transistors are programmable as a “don'tcare.” This is accomplished in one embodiment by connecting the gate ofthe transistor to the power supply for the decoder. A “don't care” (X)bit is used to reduce the number of necessary blocks of seriestransistors in a decoder such as decoder 106.

As shown in FIG. 2, transistor/contact combinations 202/220, 204/222,206/224, 208/226, and 210/228 are programmed to activate if theirrespective input bit on the bus 238 is a binary 0. Transistor/contactcombinations 212/230 and 214/232 are programmed to activate if theirrespective input bit on the bus 236 is a binary 1, andtransistor/contact combination 216/234 is programmed as an X or “don'tcare” bit.

With 8 status bits of information as in one of the embodiments of thepresent invention, and with 8 input bits of information, there are 2⁸possible combinations of each set of bits that can be used with thedecoder. In order to decode that many combinations, both normal andinverted status signals are used.

If the ROM is changed, selection of the same row, which is one ROM line,can be made with different inputs, depending upon the status bits. Forexample, if the DQ vias change, the same ROM operation is beingperformed, but with different user DQ data as input bits. If the ROMchanges without changing the decoder, the same inputs on the DQ linewill execute a different operation on the ROM. So, the ROM data are anoperation desired to be performed, and the decoder data identify whichinput must be present in order to perform exactly the desired operation.

User data from an external source is presented through the DQ inputs tothe decoder via the synch latches. All data sent to decoder is comparedto what is written or programmed into the programmable decoder. One ofthe total number of word lines in the ROM is decoded to obtain datastored in the ROM. This data, retrieved from the ROM if the inputs matchwhat is encoded into the decoder, is used in various embodiments toinitiate or perform commands to other circuitry that must perform theoutcome that the user is requesting with the input DQ bits. Some part ofthe data is used to analyze data with new inputs that will arrive at thedecoder on the next clock cycle.

A state machine, such as a Mealy or Moore Model state machine, reactsdepending upon the state it is in. The state machine moves from state tostate, depending in one embodiment upon the inputs, the actual state,and other feedback from other system circuitry such as flash memory,DRAM, and the like. Feedback is defined in one embodiment as certainconditional information. In one embodiment, if an input is A, theresulting state for that input is B. Other conditions like C exist whichcan change the state. For example, a condition such as C may indicate inone state for a given input, that the operation cannot be performed, andinstead a different operation is to be performed.

The previous state, new inputs, and feedback all determine the nextstate of the state machine. The current state is analyzed with newinputs to determine the next operations for the system to perform.Identical data input into different existing states therefore producespotentially different results based on the current state of the ROM. Thespecification sheets for ROMs contain tables of information describingall possible sequences and outcomes for various states.

In another embodiment, the transistor banks such as bank or block 200are programmable. Each of the contacts is accessible through vias in aninsulating layer. To complete a contact connection, vias are made in theinsulating layer to allow the interconnection of the contact at theappropriate via location to the gate of its transistor. If theparticular transistor/contact is to be programmed to activate if itsrespective input bit is a binary 0, then the appropriate via is drilledin a location to reach the contact hard wired to the statusb line 238.If on the other had the particular transistor/contact is to beprogrammed to activate when its respective input bit is a binary 1, anappropriate via is drilled in a location to reach the contact hard wiredto the status line 236.

In certain instances, one or more of the bits in a particular byte willnot affect the programming. For example, in a certain block, such asblock 200, the status as a binary 1 or a binary 0 of transistor 202 maynot matter. That is, all of the programming for that particular blockwill rely on some or all of the remaining transistors, but not ontransistor 202. In this instance, multiple possible programming may bemade on a single block, and the overall number of blocks may be reduced.In this instance, the transistor 202 is programmed as a “don't care”(X). If a 1 or a 0 is asserted as an input on a “don't care” line, theline gives whatever result is necessary, that is it is hard wired togive the proper response.

One instance of the use of a “don't care” bit is when two states aredifferent for only one bit. In that configuration, there is no need touse two rows as would normally be required, one for a binary 1 resultand the second for a binary 0 result. Instead, a single “don't care” isused. Forcing a don't care line to the bit that doesn't matter allowsthe use of one row of the decoder as opposed to two rows of the decoder.Since decoder line space and real estate is at a premium, this is aspace saver.

The “don't care” positions are chosen in one embodiment in first and/orlast positions for layout efficiency and compactness. While transistors202 and 216 are the only transistors shown in FIG. 3 to be programmableas “don't care” bits, any of the transistors in the series could beconfigured in another embodiment to be programmable as a “don't care.”

In fabrication of ROMs and the like, the via connections described aboveare formed in one of the last masks used. Because of this, theembodiments of the present invention allow changes to the masks andtherefore to the ROM encoding to be made very late in the fabricationprocess. In certain embodiments, all the circuit logic and ROM iscompletely fabricated before the vias must be drilled. Previously, ifthe programming of a circuit changed at any time after the fabricationprocess had begun, the entire circuit layout and subsequent generationflow would also need to be re-executed. This resulted in significantdelays in production, lost yield, and added expense of fabrication andmanufacture. With the programmable via mask and via location embodimentsdescribed herein, if the commands or ROM encoding change, the via maskcan be redesigned without re-doing the entire process. This saves timeand money in the fabrication process. All that changes is the via maskand hence the locations of the vias to be drilled.

FIG. 2A shows a schematic with three encoders, a DQ section, a feedbacksection, and a status section. However, it should be understood that thedecoder configuration is modular. More or fewer decoders are used inother embodiments without departing from the scope of the invention.

A plurality of blocks such as block 200 are used to decode multiplebytes of input data, status data, and the like, in various embodiments.A number of blocks such as block 200 are shown connected in a series ofdecoder sections 250 in FIG. 2A. Each of the decoder sections 250 issized with a number of blocks 200 to accommodate the number of inputsignal combinations into the decoder. The number of decoder sections 250is changed to accommodate the number of decoder sections necessary forthe full decoder to be operable. Since the layout of each block 200 isthe same, the embodiments of the present invention are scalable towhatever size decoder is required.

In operation, the CUI works as follows. During a pre-charge phase, allthe decoder nodes are pulled up. During the decoding phase, when theROM_READ signal is asserted, all the decoders are enabled via the extratransistor in series to the decoder transistors. In one embodiment,there are 24 transistors used to recognize the configuration of the DQinputs, status, and feedback signals, eight for each set of signals. Ifthe global input configuration for all of the transistors is matched bythe DQ inputs, the status, and the feedback, then only one of thedecoder output nodes is discharged, and a single wordline is asserted.

When the decoder asserts a ROM wordline, the ROM access begins. Standardcontrol circuitry feeds sequential timing for the ROM. A timing diagramfor operation of one embodiment of the CUI 100 is shown in FIG. 3 for abitline pre-charge phase and a following sensing phase. When theaddressed data are stored in the latches, the control circuitry switchesthe decoder and the ROM off to reduce power consumption. The signalsoutput by the latches control the next state of the CUI and also giveinformation to the WSM about the operation to be executed.

In another embodiment, the CUI and ROM are utilized in low powerdevices. Such devices include by way of example only and not by way oflimitation cellular telephones, handheld computing devices, and thelike. The assertion of the CE* and WE* signals, or a combinationthereof, in one embodiment constitutes a circuit wakeup signal to beginoperation. The cycle time for the input signals is in one embodimentapproximately 80 nanoseconds. On the other hand, the approximate timefor completion of all ROM operations, including decoding, ROM access,latching, and feedback, is approximately 40-50 nanoseconds. That leavesa significant portion of each cycle in which the ROM is normallypowered, but during which time the ROM is not performing any operations.

In one embodiment of the CUI of the present invention, the lastoperation to complete triggers on its falling edge a shutdown sequencewhich turns off power to the ROM. This stop point or trigger is giveninternally by the ROM circuitry. The last falling edge triggers theshutdown. Shutdown in one embodiment occurs within approximately 5-6nanoseconds. Power is therefore conserved in one embodiment forapproximately 20-30 nanoseconds of the cycle time, resulting insignificant power savings. The next decoding phase is awakened by a newclock signal.

In the embodiments shown, one block of transistors is used for eachwordline of the ROM. The number of transistors depends on the number ofinputs. If there are 16 inputs, 16 transistors are used. Due to signalloss in series of transistors, banks of 8 are used in one embodiment,but they can be cascaded together to accommodate more inputs. In thisway, the embodiments of the present invention are easily scalable tolarge systems of 50 or more inputs.

The various embodiments of the present invention described above arecapable of implementation in multiple different chips, for example flashmemories, DRAMs, and the like. Further, anything that can be encoded iscapable of use with the ROM. For example, any analog voltage,temperature, state of other circuitry, and the like, if encoded inbinary form, can be decoded using the decoder embodiments of the presentinvention. Then, when decoding with the decoder, different reactions tothe same input can be made depending upon the current conditions.

A method 400 for programming a decoder is shown in greater detail in theflow chart diagram of FIG. 4. Method 400 comprises fabricating aplurality of transistors connected in series in block 402, and forming aplurality of contacts for each transistor to an input or to itscomplement in block 404. The transistors are in one embodimentselectively coupleable to one of the contacts. Process flow continueswith selectively coupling the gate of each transistor to one of its pairof contacts in block 406. Coupling the gate of the transistor to acontact in one embodiment comprises making a via through an insulatinglayer in an appropriate position to access the appropriate contact, andinterconnecting the via and the transistor gate. Since making vias is ator near the back end of the fabrication process, all that is necessaryto be done following the making of the vias at the appropriate locationsis to connect the two interconnects, that of the switch terminal andthat of the gate of its transistor.

Changing a via mask to allow re-encoding of a decoder saves significanttime and money, because the via mask is one of the last masks to be usedin the process of fabricating an encoder. Further, since only the viamask needs to be changed, there is less waste of resources as well inthe implementation of the various embodiments of the present invention.

It is to be understood that the above description is intended to beillustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reading and understanding theabove description. The scope of the invention should, therefore, bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A method for re-encoding a decoder, the method comprising: changingonly via locations in an insulating layer to effect re-encoding, whereina via location defines a contact to which a gate of a transistor iscoupled.
 2. The method of claim 1, wherein changing via locationscomprises: creating a revised via mask of the decoder for a new command;and making vias through an insulating layer to create a transistor gatecontact.
 3. The method of claim 1, wherein making vias comprises:drilling vias through the insulating layer in response to the revisedvia mask; and connecting appropriate vias to each gate of the pluralityof series connected transistors.
 4. The method of claim 3, and furthercomprising: connecting the gate of a first transistor of the pluralityof series connected transistors to a supply voltage.
 5. The method ofclaim 4, wherein connecting the gate to the supply voltage changes thefirst transistor from a predetermined bit location to a do not carelocation.
 6. The method of claim 3, wherein drilling vias comprises:drilling through the insulating layer to an appropriate signal bus of aplurality of signal buses.
 7. A memory device, comprising: an array ofmemory cells; control circuitry to read, write and erase the memorycells; address circuitry to latch address signals provided on addressinput connections, and; a command user interface connected to the ROM tocontrol commands for the ROM, the CUI comprising: a decoder having aplurality of series-connected transistors whose gates are selectivelycoupled to receive either an input or its complement using vias; and aplurality of latches to latch input and output data for the command userinterface.
 8. The memory device of claim 7, wherein at least one of theseries-connected transistors is further selectively coupled to receive asupply voltage using its via.
 9. The memory device of claim 7, whereinusing the vias comprises selecting a location for the via.
 10. Thememory device of claim 7, wherein each series-connected transistor has afirst contact hard wired to the input and a second contact hard wired tothe complement of the input.
 11. The memory device of claim 10, whereinat least one of the transistors has a third contact hard wired to asupply voltage.
 12. The memory device of claim 7, wherein the decodercomprises: a plurality of decoder blocks, each decoder block comprisinga plurality of transistors connected in series, each transistor having afirst contact coupled to the input, and a second contact coupled to thecomplement of the input.
 13. The memory device of claim 7, wherein eachtransistor is capable of one selective coupling to connect the gate ofits transistor.
 14. The memory device of claim 8, wherein at least oneof the plurality of transistors is further programmable to connect tothe supply voltage to configure the transistor as a don't care.
 15. Thememory device of claim 7, wherein the decoder comprises: a first decodersection comprising: a plurality of transistors connected in series; anda plurality of contacts, each contact coupled to either the input or thecomplement of the input, wherein the vias connect a gate of a singletransistor of the plurality of transistors to either the input or to thecomplement of the input using the vias.
 16. The memory device of claim15, wherein at least one of the plurality of transistors is furtherselectively coupled to receive a supply voltage using its via.
 17. Thememory device of claim 15, wherein the decoder further comprises asecond decoder section substantially identical to the first decodersection, and connected in series with the first decoder section, thefirst and the second decoder sections to decode different inputs to thedecoder.
 18. The memory device of claim 15, wherein the decoder furthercomprises a second decoder section substantially identical to the firstdecoder section, and connected in parallel with the first decodersection, the first and the second decoder sections to decode differentinputs to the decoder.
 19. The memory device of claim 7, wherein theplurality of latches comprises: a plurality of input latches to receiveinput data and a clock signal and to output latched input data to thedecoder; a plurality of output latches to receive output data from theROM; and a plurality of status latches to receive state information fromthe ROM and to output latched status data to the decoder.
 20. The memorydevice of claim 19, wherein the input latches further receive a feedbacksignal from an external write state machine and wherein the inputlatches output latched feedback data to external circuitry.
 21. A memorydevice, comprising: an array of memory cells; control circuitry to read,write and erase the memory cells; address circuitry to latch addresssignals provided on address input connections, and; a command userinterface connected to the ROM to control commands for the ROM, the CUIcomprising: a plurality of transistors connected in series, eachtransistor having first and second contacts hard programmed to a lowlogic value and a high logic value respectively; a plurality of viaseach connectable between a gate of one of the plurality of transistorsand the first or the second contact to hard program the low logic valueor the high logic value; and a plurality of latches to latch input andoutput data for the command user interface.
 22. The memory device ofclaim 21, wherein at least one of the plurality of transistors has athird contact hard programmed to a supply voltage.
 23. The memory deviceof claim 21, and further comprising: a second plurality of transistorsconnected in series, each of the second plurality of transistors havingfirst and second contacts hard programmed to a low logic value and ahigh logic value respectively; a second plurality of vias eachconnectable between a gate of one of the second plurality of transistorsand the first or the second contact to hard program the low logic valueor the high logic value; and a second plurality of latches to latchinput and output data for the command user interface.
 24. A memorydevice, comprising: an array of memory cells; control circuitry to read,write and erase the memory cells; address circuitry to latch addresssignals provided on address input connections, and; a command userinterface connected to the ROM to control commands for the ROM, the CUIcomprising: a plurality of decoders, each decoder having a series oftransistors whose gates are selectively coupled to receive either aninput or its complement using vias; and a plurality of latches to latchinput and output data for the command user interface.
 25. The memorydevice of claim 24, wherein each decoder comprises: a plurality oftransistors connected in series, each transistor having a first contacthard wired to the input and a second contact hard wired to thecomplement of the input.
 26. The memory device of claim 24, wherein eachdecoder further comprises a plurality of decoder section, each decodersection comprising: a plurality of transistors connected in series; anda plurality of contacts, each contact coupled to either the input or thecomplement of the input, wherein the vias connect a gate of a singletransistor of the plurality of transistors to either the input or to thecomplement of the input using the vias.
 27. A memory device, comprising:an array of non-volatile memory cells; control circuitry to read, writeand erase the memory cells; address circuitry to latch address signalsprovided on address input connections, and; a decoder connected to thearray to control commands for the array, the decoder comprising: a firstdecoder section comprising: a plurality of transistors connected inseries whose gates are selectively coupled to receive either an input orits complement from one of a pair of contacts; and a pair of contactsfor each transistor, each contact coupled to the input or to thecomplement of the input through a via.
 28. The memory device of claim27, and further comprising an actuation transistor connected in serieswith the plurality of transistors, the actuation transistor enabling theplurality of transistors for a read of the plurality of transistors. 29.The memory device of claim 27, wherein the plurality of transistorscomprises the same number of transistors as there are data inputs to thedecoder.
 30. The memory device of claim 27, wherein the first or thesecond contact is accessed by forming a via to the contact.
 31. Thememory device of claim 27, wherein at least one of the series oftransistors is further selectively coupled to receive a supply voltage.32. The memory device of claim 27, and further comprising: a seconddecoder section comprising: a second plurality of transistors connectedin series whose gates are selectively coupled to receive either an inputor its complement from one of a second pair of contacts; and a pair ofcontacts for each of the plurality of second transistors, each of thesecond pairs of contacts coupled to the input or to the complement ofthe input.
 33. The memory device of claim 32, wherein the second decodersection is connected in series with the first decoder section.
 34. Thememory device of claim 32, wherein the second decoder section isconnected in parallel with the first decoder section.
 35. The memorydevice of claim 34, wherein each of the decoder sections decodes aparticular different set of inputs.
 36. The memory device of claim 32,wherein at least one of the second plurality of transistors is furtherselectively coupled to receive a supply voltage using its via.
 37. Thememory device of claim 32, and further comprising: a third decodersection comprising: a third plurality of transistors connected in serieswhose gates are selectively coupled to receive either an input or itscomplement from one of a third pair of contacts; and a pair of contactsfor each of the third plurality of transistors, each of the third pairsof contacts coupled to the input or to the complement of the input. 38.The memory device of claim 37, wherein the third decoder section isconnected in series with the first and the second decoder sections. 39.The memory device of claim 37, wherein the third decoder section isconnected in parallel with the first decoder and the second decodersections.
 40. The memory device of claim 37, wherein each of the decodersections decodes a particular different set of inputs to the decoder.41. The memory device of claim 27, wherein the first decoder sectiondecodes data inputs to the programmable decoder.
 42. The memory deviceof claim 32, wherein the first decoder section decodes data inputs tothe programmable decoder and wherein the second decoder section decodesstatus inputs to the programmable decoder.
 43. The memory device ofclaim 37, wherein the first decoder section decodes data inputs to theprogrammable decoder, and wherein the second decoder section decodesstatus inputs to the programmable decoder, and wherein the third decodersection decodes feedback inputs to the programmable decoder.
 44. Thememory device of claim 38, wherein at least one of the third pluralityof transistors is selectively coupled to a supply voltage.
 45. A memorydevice, comprising: an array of non-volatile memory cells; controlcircuitry to read, write and erase the memory cells; address circuitryto latch address signals provided on address input connections, and; aprogrammable decoder connected to the array to control commands for thearray, the programmable decoder comprising: a first decoder sectioncoupled to decode data from the first input, the first decoder sectioncomprising: a plurality of transistors connected in series; and aplurality of contacts, each contact coupled to either the input or thecomplement of the input, wherein the vias connect a gate of a singletransistor of the plurality of transistors to either the input or to thecomplement of the input; and a second decoder section substantiallyidentical to the first decoder section, and connected in series with thefirst decoder section, the second decoder section coupled to decode datafrom the second input.
 46. The memory device of claim 45, and furthercomprising a plurality of latches to latch input and output data for theprogrammable decoder, wherein the plurality of latches comprises: aplurality of input latches to receive input data and a clock signal andto output latched input data to the decoder; a plurality of outputlatches to receive output data from a read only memory; and a pluralityof status latches to receive state information from the read only memoryand to output latched status data to the decoder.